In semiconductor manufacturing, as submicron device size has become increasingly common, Shallow Trench Isolation (STI), because of the greater density of devices that can be placed on a substrate and improved planarity, has proven superior to the Local Oxidation of Silicon (LOCOS) technology. However, one problem that exists with STI is the loss of oxide at the top inside corners of the isolation trenches, ultimately resulting in parasitic current leakage for the active devices disposed on the substrate.
One prior art method for solving the "corners" effect at the trench edge is taught by Fazan et al (U.S. Pat. Nos. 5,433,794; 5,733,383) whereby an isolating material extends over the edges of the trench. Referring to FIG. 1, an insulating layer 5 has been deposited over a semiconductor substrate 1 on which has been deposited a pad oxide layer 2 and which contains a trench lined with a thermal oxide 2a and filled with an isolating material 4. The spacers 5 shown in FIG. 2 result after a dry etching process, the spacers being located at the corners of the trench and having similar chemical properties to the isolation material 4. Referring to FIG. 3, a wet pad oxide etch causes the isolating material 4 to combine with the spacers 5 to form the cap 4a, which extends beyond the edges of the trench.
Certain other patents also address the subject of leakage at the upper corners of isolation trenches. For instance, Pan et al (U.S. Pat. Nos. 5,834,358; 5,763,932) teaches STI planarization processes using an etch back; Tseng (U.S. Pat. No. 5,801,082) planarizes an STI oxide using spin-on glass (SOG) spacers and an etch back; Abiko (U.S. Pat. No. 5,677,233) shows an STI planarization process that reduces oxide loss at trench corners using an oxide spacer; and Lee et al (U.S. Pat. No. 5,229,316) describes a process for forming an STI using a planarizing etch of a sacrificial layer. However, all of the etchback approaches from the prior art involve some kind of oxide deposition, either through chemical vapor deposition or spin-on, which adds to the complexity of the process. Moreover, oxide etchback processes will inevitably expose the substrate in the plasma, which can degrade the quality of the silicon substrate for subsequent device formation.